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a preliminary technical data adsp-21160 dsp microcomputer this information applies to a product under development. its characteristics and specifications are subject to change without notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. one technology way http://www.analog.com/dsp p.o. box 9106 tel: 1-800-analog-d norwood ma 02062-9106 fax: 1-781-461-3010 u.s.a . ? analog devices inc., 1998 rev. pre summary ? high performance 32-bit dsp?applications in audio, medical, military, graphics, imaging, and communication super harvard architecture?four independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead i/o backwards compatible?assembly source level compatible with code for adsp-2106x dsps single-instruction-multiple-data (simd) com- putational architecture?two 32-bit ieee float- ing-point computation units, each with a multiplier, alu, shifter, and register file integrated peripherals?integrated i/o proces- sor, 4 mbit on-chip dual-ported sram, glueless multiprocessing features, and ports (serial, link, external bus, & jtag) key features 80 mhz (12.5 ns) or 100 mhz (10 ns) core instruction rate single-cycle instruction execution, including simd operations in both computational units 600 mflops peak and 400 mflops sustained performance (based on fir) dual data address generators (dags) with modulo and bit-reverse addressing zero-overhead looping and single-cycle loop set- up, providing efficient program sequencing ieee 1149.1 jtag standard test access port and on-chip emulation 400-ball 27 27mm pbga package figure 1 adsp-21160 functional block diagram mult alu barrel shifter data register file (pey) 16 x 40-bit mult alu barrel shifter data register file (pex) 16 x 40-bit serial ports (2) link ports (6) 4 6 6 60 iop registers ( memory mapped) control, status, & data buffers i/o processor dma controller timer instruction cache 32 x 48-bit addr data data data addr addr data addr two independent dual-ported blocks processor port i/o port b l o c k 0 b l o c k 1 dual-ported sram jtag test & emulation 6 host port addr bus mux ioa 18 iod 64 multiprocessor interface external port data bus mux 64 32 32 pm address bus dm address bus pm data bus dm data bus bus connect (px) dag1 8x4x32 32 16/32/40/48/64 32/40/64 core processor program sequencer dag2 8x4x32
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 2 rev. pre features (continued) single instruction multiple data (simd) architecture provides: two computational processing elements concurrent execution--each processing element executes the same instruction, but oper- ates on different data code compatibility--at assembly level, uses the same instruction set as the adsp-2106x sharcs parallelism in busses and computational units allows: single-cycle execution (with or without simd) of: a multiply operation, an alu opera- tion, a dual memory read or write, and an instruction fetch transfers between memory and core at up to four 32-bit floating- or fixed-point words per cycle accelerated fft butterfly computation through a multiply with add and subtract 4 mbit on-chip dual-ported sram for independent access by core processor, host, and dma dma controller supports: 14 zero-overhead dma channels for transfers between adsp-21160 internal memory and external memory, external peripherals, host processor, serial ports, or link ports 64-bit background dma transfers at core clock speed, in parallel with full-speed proces- sor execution 700 mbytes/s transfer rate over iop bus host processor interface to 16- and 32-bit microprocessors 4 gigaword address range for off-chip memory memory interface supports programmable wait state generation and page-mode for off-chip mem- ory multiprocessing support provides: glueless connection for scalable dsp multiprocessing architecture distributed on-chip bus arbitration for parallel bus connect of up to six adsp-21160s plus host six link ports for point-to-point connectivity and array multiprocessing 400 mbytes/s transfer rate over parallel bus 600 mbytes/s transfer rate over link ports serial ports provide: two 50 mbit/s synchronous serial ports with companding hardware independent transmit and receive functions tdm support for t1 and e1 interfaces 64-bit wide synchronous external port provides: glueless connection to asynchronous and sbsram external memories up to 50 mhz operation
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 3 rev. pre general description the adsp-21160 sharc dsp is the first processor in a new family featuring analog devices ? super harvard architecture. easing portability, the adsp-21160 is application source code compatible with first generation adsp-2106x sharcs in sisd (single instruction, single data) mode. to take advantage of the processor ? s simd (single instruction, multiple data) capability, some code changes are needed. like other sharcs, the adsp-21160 is a 32-bit processor that is optimized for high performance dsp applications. the adsp-21160 includes a 80 or 100 mhz core, a dual-ported on-chip sram, an integrated i/o processor with multiprocessing support, and multiple internal busses to eliminate i/o bottlenecks. the adsp-21160 introduces single-instruction-multiple-data (simd) processing. using two computational units (adsp-2106x sharcs have one), the adsp-21160 can double performance versus the adsp-2106x on a range of dsp algorithms. fabricated in a state of the art, high speed, low power cmos process, the adsp-21160 has a 10 ns (or 12.5 ns) instruction cycle time. with its simd computational hardware running at 100 mhz, the 21160 can perform 600 million math operations per second. table 1 shows performance benchmarks for the adsp-21160. the adsp-21160 continues sharc ? s industry leading standards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. these features include a 4 mbit dual ported sram memory, host processor interface, i/o processor that supports 14 dma channels, two serial ports, six link ports, external parallel bus, and glueless multiprocessing. figure 1 shows a block diagram of the adsp-21160, illustrating the following architectural features: two processing elements, each made up of an alu, multiplier, shifter and data register file data address generators (dag1, dag2) program sequencer with instruction cache pm and dm buses capable of supporting four 32-bit data transfers between memory and the core every core processor cycle interval timer table 1 adsp-21160 benchmarks (at 100 mhz and 80 mhz) benchmark algorithm speed (at 100 mhz) speed (at 80 mhz) 1024 point complex fft (radix 4, with reversal) 92 us 115 us fir filter (per tap) 5 ns 6.25 ns iir filter (per biquad) 20 ns 25 ns matrix multiply (pipelined) [3x3] * [3x1] [4x4] * [4x1] 45 ns 80 ns 56.25 ns 100 ns divide (y/x) 30 ns 37.5 ns inverse square root 45 ns 56.25 ns dma transfer rate 700 mbytes/s 560 mbytes/s
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 4 rev. pre on-chip sram (4 mbit) external port that supports: interfacing to off-chip memory peripherals glueless multiprocessing support for six adsp-21160 sharcs host port dma controller serial ports and link ports jtag test access port figure 2 shows a typical single-processor system. a multi-processing system appears in figure 5 . figure 2 adsp-21160 system adsp-21160 family core architecture the adsp-21160 includes the following architectural features of the adsp-21100 family core. the adsp-21160 is code compatible at the assembly level with the adsp-21060, adsp-21061, and adsp-21062. simd computational engine the adsp-21160 contains two computational processing elements that operate as a single instruction multiple data (simd) engine. the processing elements are referred to as pex and pey and each contains an alu, multiplier, shifter and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. this architecture is efficient at executing math intensive dsp algorithms. 3 4 reset jtag 6 adsp-2116x bms clock link devices (6 m a x) (optional) cs boot eprom (optional) addr memory and peripherals (o ptio nal) oe data dm a device (optional) data addr data host processor in terfa ce (o ptio nal) serial device (optional) cs rdx page clkout ack br1-6 dmar1-2 serial device (optional) clkin irq2-0 lxc lk tc lk0 rpba 4 clk_cfg3-0 eboot lboot fla g 3-0 tim ex p lxa c k lxda t7-0 dr0 dt0 rsf0 tfs0 rclk0 tc lk1 dr1 dt1 rsf1 tfs1 rclk1 id2-0 serial device (optional) serial device (optional) pa redy hbg hbr dmag1-2 sbts ms3-0 wrx data63-0 data addr cs ack we addr31-0 data c ontrol a ddress cif brst
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 5 rev. pre entering simd mode also has an effect on the way data is transferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the processing elements. because of this requirement, entering simd mode also doubles the bandwidth between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier and shifter. these units perform single-cycle instructions. the three units within in each processing element are arranged in parallel, maximizing computational throughput. single multi-function instructions execute parallel alu and multiplier operations. in simd mode, the parallel alu and multiplier operations occur in both processing elements. these computation units support ieee 32-bit single-precision floating-point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats. data register file a general purpose data register file is contained in each processing element. the register files transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-register (16 primary, 16 secondary) register files, combined with the adsp-21100 enhanced harvard architecture, allows unconstrained data flow between computation units and internal memory. the registers in pex are referred to as r0-r15 and in pey as s0-s15. single-cycle fetch of instruction and four operands the adsp-21160 features an enhanced harvard architecture in which the data memory (dm) bus transfers data and the program memory (pm) bus transfers both instructions and data (see figure 1 ). with the adsp-21160 ? s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands and an instruction (from the cache), all in a single cycle. instruction cache the adsp-21160 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. the cache is selective ? only the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and fft butterfly processing. data address generators with hardware circular buffers the adsp-21160 ? s two data address generators (dags) are used for indirect addressing and let you implement circular data buffers in hardware. circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of the adsp-21160 contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). the dags automatically handle address pointer wrap-around, reducing overhead, increasing performance, and simplifying implementation. circular buffers can start and end at any memory location.
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 6 rev. pre flexible instruction set the 48-bit instruction word accommodates a variety of parallel operations, for concise programming. for example, the adsp-21160 can conditionally execute a multiply, an add, and subtract, in both processing elements, while branching, all in a single instruction. adsp-21160 memory and i/o interface features augmenting the adsp-21100 family core, the adsp-21160 adds the following architectural features: dual-ported on-chip memory the adsp-21160 contains four megabits of on-chip sram, organized as two blocks of 2 mbits each, which can be configured for different combinations of code and data storage. each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o processor. the dual-ported memory in combination with 3 separate on-chip buses allow two data transfers from the core and one from i/o processor, in a single cycle. on the adsp-21160, the memory can be configured as a maximum of 128k words of 32-bit data, 256k words of 16-bit data, 85k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to four megabits. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the dm bus for transfers, and the other block stores instructions and data, using the pm bus for transfers. using the dm bus and pm bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. in this case, the instruction must be available in the cache. off-chip memory and peripherals interface the adsp-21160 ? s external port provides the processor ? s interface to off-chip memory and peripherals. the 4-gigaword off-chip address space is included in the adsp-21160 ? s unified address space. the separate on-chip buses ? for pm addresses, pm data, dm addresses, dm data, i/o addresses, and i/o data ? are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 64-bit data bus. the lower 32 bits of the external data bus connect to even addresses and the upper 32 bits of the 64 connect to odd addresses. every access to external memory is based on an address that fetches a 32 bit word, and with the 64 bit bus, two address locations can be accessed at once. when fetching an instruction from external memory, two 32 bit data locations are being accessed (16 bits are unused). figure 4 shows the alignment of various accesses to external memory. the external port supports asynchronous, synchronous, and synchronous burst accesses. zbt synchronous burst sram can be interfaced gluelessly. addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. separate control lines are also generated for simplified addressing of page-mode dram. the adsp-21160 provides programmable memory wait states and external memory acknowledge controls to allow interfacing to dram and peripherals with variable access, hold, and disable time requirements
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 7 rev. pre figure 3 adsp-21160 memory map dma controller the adsp-21160 ? s on-chip dma controller allows zero-overhead data transfers without processor intervention. the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously executing its program instructions. dma transfers can occur between the adsp-21160 ? s internal memory and external memory, external peripherals, or a host processor. dma transfers can also occur between the adsp-21160 ? s internal memory and its serial ports or link ports. external bus packing to 16-, 32-, 48-, or 64- bit words is performed during dma transfers. fourteen channels of dma are available on the adsp-21160 ? six via the link ports, four via the serial ports, and four via the processor ? s external port (for either host processor, other adsp-21160s, memory or i/o transfers). programs can be downloaded to the adsp-21160 using dma transfers. asynchronous off-chip peripherals can control two dma channels using dma request/grant lines (dmar1-2 , dmag1-2 ). other dma features include interrupt generation upon completion of dma transfers, two-dimensional dma, and dma chaining for automatic linked dma transfers. 0x00 0000 0x02 0000 0x04 0000 0x08 0000 0x10 0000 0x20 0000 0x30 0000 0x40 0000 0x50 0000 0x60 0000 0x70 0000 0x7f ffff 0x80 0000 0xffff ffff internal memory space multi- external memory space processor memory space iop reg?s long word normal word short word internal space internal space internal space internal space internal space internal space broadcast all dsps bank 0 bank 1 bank 2 bank 3 non-banked ms 0 ms 1 ms 2 ms 3 memory (id=011) (id=100) memory (id=101) memory memory (id=110) write to (id=111) memory (id=010) memory (id=001)
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 8 rev. pre figure 4 adsp-21160 external data alignment options multiprocessing the adsp-21160 offers powerful features tailored to multi-processing dsp systems. the external port and link ports provide integrated glueless multiprocessing support. the external port supports a unified address space (see figure 3 ) that allows direct interprocessor accesses of each adsp-21160 ? s internal memory. distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six adsp-21160s and a host processor. master processor change over incurs only one cycle of overhead. bus arbitration is selectable as either fixed or rotating priority. bus lock allows indivisible read-modify-write sequences for semaphores. a vector interrupt is provided for interprocessor commands. maximum throughput for interprocessor data transfer is 400 mbytes/s over the external port. broadcast writes allow simultaneous transmission of data to all adsp-21160s and can be used to implement reflective semaphores. six link ports provide for a second method of multiprocessing communications. each link port can support communications to another 21160. using the links a large multiprocessor system can be constructed in a 2d or 3d fashion. the adsp-21160 at 100 mhz has a maximum throughput for interprocessor communications over the links of 600 mbytes per second. you can use the link ports and cluster multiprocessing concurrently or independently. data63-0 63 55 47 39 31 23 15 7 0 rdh/wrh rdl/wrl eprom 16-bit packed 32-bit packed 64-bit tran sfer fo r 40-bit ext. prec. 64 -bit tra n sfer fo r 4 8-bit in str u c tio n fetc h restricted dma, host, eprom data alignments: 64-bit long word, simd, dma, iop register transfers 32-bit normal word (even addr) 32-bit normal word (o dd a dd r) byte 0 byte 7
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 9 rev. pre figure 5 adsp-21160 shared memory multiprocessing system addr31-0 data63-0 pa bms control adsp-2116x #1 5 pa br1 , br3-6 br2 control adsp-2116x #2 addr31-0 data63-0 pa br1-2 , br4-6 br3 control adsp-2116x #3 5 id2-0 reset rpba clkin adsp-2116x #6 adsp-2116x #5 adsp-2116x #4 clock reset addr data host processor in terfa ce (o ptio na l) ack global memory and peripherals (o ptio na l) oe addr data cs addr data boot eprom (o ptio na l) rdx ms3-0 sbts clkout cs ack addr31-0 data63-0 id2-0 reset rpba clkin id2-0 reset rpba clkin 3 001 page 3 010 3 011 br1 br2-6 redy hbg hbr cs we wrx 5 control addres s data control addres s data
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 10 rev. pre link ports the adsp-21160 features six 8-bit link ports that provide additional i/o capabilities. with the capability of running at 100 mhz rates, each link port can support 100 mbytes/s. link port i/o is especially useful for point-to-point interprocessor communication in multiprocessing systems. the link ports can operate independently and simultaneously, with a maximum data throughput of 600 mbytes/s. link port data is packed into 48- or 32-bit words, and can be directly read by the core processor or dma-transferred to on-chip memory. each link port has its own double-buffered input and output registers. clock/acknowledge handshaking controls link port transfers. transfers are programmable as either transmit or receive. serial ports the adsp-21160 features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. the serial ports can operate up to half the clock rate of the core, providing each with a maximum data rate of 50 mbit/s. independent transmit and receive functions provide greater flexibility for serial communications. serial port data can be automatically transferred to and from on-chip memory via a dedicated dma. each of the serial ports offers a tdm multichannel mode. the serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. they offer selectable synchronization and transmit modes as well as optional -law or a-law companding. serial port clocks and frame syncs can be internally or externally generated. host processor interface the adsp-21160 host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with little additional hardware required. the host interface is accessed through the adsp-21160 ? s external port and is memory-mapped into the unified address space. four channels of dma are available for the host interface; code and data transfers are accomplished with low software overhead. the host processor requests the adsp-21160 ? s external bus with the host bus request (hbr ), host bus grant (hbg ), and ready (redy) signals. the host can directly read and write the internal memory of the adsp-21160, and can access the dma channel setup and mailbox registers. vector interrupt support provides efficient execution of host commands. program booting the internal memory of the adsp-21160 can be booted at system power-up from either an 8-bit eprom, a host processor, or through one of the link ports. selection of the boot source is controlled by the bms (boot memory select), eboot (eprom boot), and lboot (link/host boot) pins. 32-bit and 16-bit host processors can be used for booting. phased locked loop the adsp-21160 uses an on chip pll to generate the internal clock for the core. ratios of 2:1, 3:1, and 4:1 between the core and clkin are supported. the clk_cfg pins are used to select the ratio. the clkin rate is the rate at which the synchronous external port operates. power supplies the adsp-21160 has separate power supply connections for the internal (v ddint ), external (v ddext ), and analog (av dd /agnd) power supplies. the internal and analog supplies must meet the 2.5v requirement. the external supply must meet the 3.3v requirement. all external supply pins must be connected to the same supply.
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 11 rev. pre note that the analog supply (av dd ) powers the adsp-21160 ? s clock generator pll. to produce a stable clock, you must provide an external circuit to filter the power input to the av dd pin. place the filter as close as possible to the pin. for an example circuit, see figure 6 . to prevent noise coupling, use a wide trace for the analog ground (agnd) signal and install a decoupling capacitor as close as possible to the pin. figure 6 analog power (av dd ) filter circuit development tools the adsp-21160 is supported with a complete set of visualdsp ? software and hardware development tools, including the ez-ice ? in-circuit emulator and development software. the same ez-ice hardware that you use for the adsp-21060/62, also fully emulates the adsp-21160. both the sharc development tools family and the visualdsp integrated project management and debugging environment support the adsp-21160. the visualdsp project management environment enables you to develop and debug an application from within a single integrated program. the sharc development tools include an easy to use assembler that is based on an algebraic syntax; an assembly library/librarian; a linker; a loader; a cycle-accurate, instruction-level simulator; a c compiler; and a c run-time library that includes dsp and mathematical functions. debugging both c and assembly programs with the visual dsp debugger, you can: view mixed c and assembly code insert break points set conditional breakpoints on registers, memory, and stacks trace instruction execution profile program execution fill and dump memory source level debugging create custom debugger windows the visualdsp ide lets you define and manage dsp software development. its dialog boxes and property pages enable you to configure and manage all of the sharc development tools, including the syntax highlighting in the visualdsp editor. this capability lets you: control how the development tools process inputs and generate outputs. maintain a one-to-one correspondence with the tool ? s command line switches. the ez-ice emulator uses the ieee 1149.1 jtag test access port of the adsp-21160 processor to monitor and control the target board processor during emulation. the ez-ice provides full-speed v ddint av dd agnd 0.01 f 0.1 f 10 ?
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 12 rev. pre emulation, allowing inspection and modification of memory, registers, and processor stacks. non-intrusive in-circuit emulation is assured by the use of the processor ? s jtag interface ? the emulator does not affect target system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hardware tools include sharc pc plug-in cards, multiprocessor sharc vme boards, and daughter and modules with multiple sharcs ? and additional memory. these modules are based on the sharcpac ? module specification. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. additional information this data sheet provides a general overview of the adsp-21160 architecture and functionality. for detailed information on the adsp-21100 family core architecture and instruction set, refer to the adsp-21160 technical specification, revision 3.0. pin function descriptions adsp-21160 pin definitions are listed below. inputs identified as synchronous (s) must meet timing requirements with respect to clkin (or with respect to tck for tms, tdi). inputs identified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). unused inputs should be tied or pulled to vdd or gnd, except for addr31-0, data63-0, flag3-0, and inputs that have internal pull-up or pull-down resistors (pa , ack, brst, page, clkout, ms 3-0, rdx , wrx , dmarx , dmagx , dtx, drx, tclkx, rclkx, lxdat7-0, lxclk, lxack, tms, trst and tdi)--these pins can be left floating. these pins have a logic-level hold circuit (only enabled on the adsp-21160 with id2-0=00x) that prevents input from floating internally. the following symbols appear in the type column of table 2 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drain, and t = three-state (when sbts is asserted, or when the adsp-21160 is a bus slave). table 2 pin descriptions pin type function addr31-0 i/o/t external bus address . the adsp-21160 outputs addresses for external memory and peripherals on these pins. in a multiprocessor system the bus master outputs addresses for read/writes of the internal memory or iop registers of other adsp-21160s. the adsp-21160 inputs addresses when a host processor or multiprocessing bus master is reading or writing its internal memory or iop registers. a keeper latch on the dsp ? s addr31-0 pins maintains the input at the level it was last driven (only enabled on the adsp-21160 with id 2-0=00x). data63-0 i/o/t external bus data . the adsp-21160 inputs and outputs data and instructions on these pins. pull-up resistors on unused data pins are not necessary. a keeper latch on the dsp ? s data63-0 pins maintains the input at the level it was last driven (only enabled on the adsp-21160 with id2-0=00x).
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 13 rev. pre ms3-0 o/t memory select lines . these outputs are asserted (low) as chip selects for the corresponding banks of external memory. memory bank size must be defined in the syscon control register. the ms3-0 outputs are decoded memory address lines. in asynchronous access mode, the ms3-0 outputs transition with the other address outputs. in synchronous access modes, the ms3-0 outputs assert with the other address lines; however, they de-assert after the first clkin cycle in which ack is sampled asserted. rdl i/o/t memory read low strobe. rdl is asserted whenever adsp-21160 reads from the low word of external memory or from the internal mem- ory of other adsp-21160s. external devices, including other adsp-21160s, must assert rdl for reading from the low word of adsp-21160 internal memory. in a multiprocessing system, rdl is driven by the bus master. rdh i/o/t memory read high strobe. rdh is asserted whenever adsp-21160 reads from the high word of external memory or from the internal mem- ory of other adsp-21160s. external devices, including other adsp-21160s, must assert rdh for reading from the high word of adsp-21160 internal memory. in a multiprocessing system, rdh is driven by the bus master. wrl i/o/t memory write low strobe. wrl is asserted when adsp-21160 writes to the low word of external memory or internal memory of other adsp-21160s. external devices must assert wrl for writing to adsp-21160's low word of internal memory. in a multiprocessing sys- tem, wrl is driven by the bus master. wrh i/o/t memory write high strobe. wrh is asserted when adsp-21160 writes to the high word of external memory or internal memory of other adsp-21160s. external devices must assert wrh for writing to adsp-21160's high word of internal memory. in a multiprocessing sys- tem, wrh is driven by the bus master. brst i/o/t sequential burst access. brst is asserted by adsp-21160 or a host to indicate that data associated with consecutive addresses is being read or written. a slave device samples the initial address and increments an internal address counter after each transfer. the incremented address is not pipelined on the bus. if the burst access is a read from host to adsp-21160, adsp-21160 increments the address automatically as long as brst is asserted. brst is asserted after the initial access of a burst transfer. it is asserted for every cycle after that, except for the last data request cycle (denoted by rdx or wrx asserted and brst negated). a keeper latch on the dsp ? s brst pin maintains the input at the level it was last driven (only enabled on the adsp-21160 with id2- 0=00x). table 2 pin descriptions (continued) pin type function
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 14 rev. pre page o/t dram page boundary . the adsp-21160 asserts this pin to signal that an external dram page boundary has been crossed. dram page size must be defined in the adsp-21160's memory control register (wait). dram can only be implemented in external memory bank 0; the page signal can only be activated for bank 0 accesses. in a multiprocessing sys- tem page is output by the bus master. a keeper latch on the dsp ? s page pin maintains the output at the level it was last driven (only enabled on the adsp-21160 with id 2-0=00x). ack i/o/s memory acknowledge . external devices can de-assert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. the adsp-21160 deasserts ack as an output to add wait states to a synchronous access of its internal memory. a keeper latch on the dsp ? s ack pin maintains the input at the level it was last driven (only enabled on the adsp-21160 with i d2-0=00x). sbts i/s suspend bus & three-state . external devices can assert sbts (low) to place the external bus address, data, selects, and strobes in a high imped- ance state for the following cycle. if the adsp-21160 attempts to access external memory while sbts is asserted, the processor will halt and the memory access will not be completed until sbts is deasserted. sbts should only be used to recover from host processor/adsp-21160 dead- lock or used with a dram controller. irq2-0 i/a interrupt request lines . these are sampled on the rising edge of clkin and may be either edge-triggered or level-sensitive. flag3-0 i/o/a flag pins . each is configured via control bits as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. timexp o timer expired . asserted for four clkin cycles when the timer is enabled and tcount decrements to zero. hbr i/a host bus request . must be asserted by a host processor to request con- trol of the adsp-21160's external bus. when hbr is asserted in a multi- processing system, the adsp-21160 that is bus master will relinquish the bus and assert hbg . to relinquish the bus, the adsp-21160 places the address, data, select, and strobe lines in a high impedance state. hbr has priority over all adsp-21160 bus requests (br6-1 ) in a multiprocessing system. hbg i/o host bus grant . acknowledges an hbr bus request, indicating that the host processor may take control of the external bus. hbg is asserted (held low) by the adsp-21160 until hbr is released. in a multiprocess- ing system, hbg is output by the adsp-21160 bus master and is moni- tored by all others. cs i/a chip select . asserted by host processor to select the adsp-21160. table 2 pin descriptions (continued) pin type function
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 15 rev. pre redy o (o/d) host bus acknowledge . the adsp-21160 deasserts redy (low) to add waitstates to a host access when cs and hbr inputs are asserted. dmar1 i/a dma request 1 (dma channel 11). asserted by external port devices to request dma services. dmar2 i/a dma request 2 (dma channel 12). asserted by external port devices to request dma services. dmag1 o/t dma grant 1 (dma channel 11). asserted by adsp-21160 to indicate that the requested dma starts on the next cycle. driven by bus master only. dmag2 o/t dma grant 2 (dma channel 12). asserted by adsp-21160 to indicate that the requested dma starts on the next cycle. driven by bus master only. br6-1 i/o/s multiprocessing bus requests . used by multiprocessing adsp-21160s to arbitrate for bus mastership. an adsp-21160 only drives its own brx line (corresponding to the value of its id2-0 inputs) and monitors all others. in a multiprocessor system with less than six adsp-21160s, the unused brx pins should be pulled high; the processor's own brx line must not be pulled high or low because it is an output. id2-0 i multiprocessing id . determines which multiprocessing bus request (br1 - br6 ) is used by adsp-21160. id = 001 corresponds to br1 , id = 010 corresponds to br2 , and so on. use id = 000 or id = 001 in single-processor systems. these lines are a system configuration selection which should be hardwired or only changed at reset. rpba i/s rotating priority bus arbitration select . when rpba is high, rotating priority for multiprocessor bus arbitration is selected. when rpba is low, fixed priority is selected. this signal is a system configuration selection which must be set to the same value on every adsp-21160. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every adsp-21160. pa i/o/t priority access . asserting its pa pin allows an adsp-21160 bus slave to interrupt background dma transfers and gain access to the external bus. pa is connected to all adsp-21160s in the system. if access priority is not required in a system, the pa pin should be left unconnected. dtx o data transmit (serial ports 0, 1). each dt pin has a 50 k ? internal pull-up resistor. drx i data receive (serial ports 0, 1). each dr pin has a 50 k ? internal pull-up resistor. tclkx i/o transmit clock (serial ports 0, 1). each tclk pin has a 50 k ? internal pull-up resistor. table 2 pin descriptions (continued) pin type function
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 16 rev. pre rclkx i/o receive clock (serial ports 0, 1). each rclk pin has a 50 k ? internal pull-up resistor. tfsx i/o transmit frame sync (serial ports 0, 1). rfsx i/o receive frame sync (serial ports 0, 1). lxdat7-0 i/o link port data (link ports 0-5). each lxdat pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lctl0-1 register. lxclk i/o link port clock (link ports 0-5). each lxclk pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lctl0-1 register. lxack i/o link port acknowledge (link ports 0-5). each lxack pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lcom register. eboot i eprom boot select . for a description of how this pin operates, see the table in the bms pin description. this signal is a system configuration selection that should be hardwired. lboot i link boot . for a description of how this pin operates, see the table in the bms pin description. this signal is a system configuration selection that should be hardwired. bms i/o/t boot memory select . serves as an output or input as selected with the eboot and lboot pins; see table below. this input is a system con- figuration selection that should be hardwired. eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select.) 0 0 1 (input) host processor 0 1 1 (input) link port 0 0 0 (input) no booting. processor executes from external memory. 0 1 0 (input) reserved 1 1 x (input) reserved clkin i local clock in. clkin is the adsp-21160 clock input. the adsp-21160 external port cycles at the frequency of clkin. the instruction cycle rate is a multiple of the clkin frequency; it is pro- grammable at powerup. clkin may not be halted, changed, or operated below the specified frequency. table 2 pin descriptions (continued) pin type function
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 17 rev. pre clk_cfg3-0 i core/clkin ratio control. adsp-21160 core clock (instruction cycle) rate is equal to n x clkin where n is user selectable to 2, 3, or 4, using the clk_cfg3-0 inputs. clkout o/t local clock out. clkout is driven at the clkin frequency by the current bus master. this output is three-stated when the adsp-21160 is not the bus master, or when the host controls the bus (hbg asserted). a keeper latch on the dsp ? s clkout pin maintains the output at the level it was last driven (only enabled on the adsp-21160 with id2-0=00x). reset i/a processor reset . resets the adsp-21160 to a known state and begins execution at the program memory location specified by the hardware reset vector address. the reset input must be asserted (low) at power-up. tck i test clock (jtag) . provides a clock for jtag boundary scan. tms i/s test mode select (jtag) . used to control the test state machine. tms has a 20 k ? internal pull-up resistor. tdi i/s test data input (jtag) . provides serial data for the boundary scan logic. tdi has a 20 k ? internal pull-up resistor. tdo o test data output (jtag) . serial scan output of the boundary scan path. trst i/a test reset (jtag) . resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-21160. trst has a 20 k ? internal pull-up resistor. emu o (o/d) emulation status . must be connected to the adsp-21160 ez-ice tar- get board connector only. emu has a 50 k ? internal pullup resistor. cif o core instruction fetch. signal is active low when an external instruction fetch is performed. driven by bus master only. three-state when host is bus master. vddint p core power supply. nominally +2.5 v dc and supplies the dsp ? s core processor. (40 pins). vddext p i/o power supply ; nominally +3.3 v dc. (46 pins). avdd p analog power supply ; nominally +2.5 v dc and supplies the dsp ? s internal pll (clock generator). this pin has the same specifications as vddint, except that added filtering circuitry is required. for more information, see ? power supplies ? on page 10. agnd g analog power supply return . gnd g power supply return . (83 pins). table 2 pin descriptions (continued) pin type function
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 18 rev. pre target board connector for ez-ice probe the adsp-21160 ez-ice emulator uses the ieee 1149.1 jtag test access port of the adsp-21160 to monitor and control the target board processor during emulation. the ez-ice probe requires the adsp-21160's clkin, tms, tck, trst, tdi, tdo, emu, and gnd signals be made accessible on the target system via a 14-pin connector (a 2 row 7 pin strip header) such as that shown in figure 5. the ez-ice probe plugs directly onto this connector for chip-on-board emulation. you must add this connector to your target board design if you intend to use the adsp-21160 ez-ice. the total trace length between the ez-ice connector and the furthest device sharing the ez-ice jtag pins should be limited to 15 inches maximum for guaranteed operation. this length restriction must include ez-ice jtag signals which are routed to one or more adsp-21160 devices, or a combination of adsp-21160 devices and other jtag devices on the chain. the 14-pin, 2-row pin strip header is keyed at the pin 3 location --pin 3 must be removed from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spacing should be 0.1 0.1 inches. pin strip headers are available from vendors such as 3m, mckenzie and samtec. the btms, btck, btrst and btdi signals are provided so the test access port can also be used for board-level testing. when the connector is not being used for emulation, place jumpers between the bxxx pins and the xxx pins. if the test access port will not be used for board testing, tie btrst and btck pins to gnd. the trst pin must be asserted after power-up (through btrst on the connector) or held low for proper operation of the adsp-21160. none of the bxxx pins (pins 5, 7, 9, 11) are connected on the ez-ice probe. figure 7 target board connector for adsp-21160 ez-ice emulator (jumpers in place) nc do not connect . reserved pins which must be left open and uncon- nected. (5 pins). table 2 pin descriptions (continued) pin type function top view 13 14 11 12 910 9 78 56 34 12 emu clkin (optional) tm s tc k trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 19 rev. pre the jtag signals are terminated on the ez-ice probe as follows: figure 8 shows jtag scan path connections for systems that contain multiple adsp-21160 processors connecting clkin to pin 4 of the ez-ice header is optional. the emulator only uses clkin when directed to perform operations such as starting, stopping in a and synchronous manner. if you do not need these operations to occur synchronously on the multiple processors, simply tie pin 4 of the ez-ice header to ground. figure 8 jtag scan path connections for multiple adsp-21160 systems table 3 ez-ice emulator probe terminations signal termination tms driven through 22 ? resistor (16 ma driver) tck driven at 10 mhz through 22 ? resistor (16 ma driver) trst active low driven through 22 ? resistor (16 ma driver) (pulled up by on-chip 20 k ? resistor); trst is driven low until the ez-ice probe is turned on by the emulator at software start-up. after software start-up, trst is driven high. tdi driven by 22 ? resistor (16 ma driver) tdo one ttl load, split (160/220) clkin one ttl load, split (160/220) emu active low 4.7 k ? pull-up resistor, one ttl load (open-drain output from the dsp) adsp-21160 #1 jtag device (o ptio n al) adsp-21160 n tdi ez-ice jtag connector other jtag controller optional emu tm s tc k tdo clkin trst tdi tdo tdi tdo tdo tdi tm s tc k trst tm s tc k tm s tc k emu trst emu trst
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 20 rev. pre figure 9 jtag clocktree for multiple adsp-21160 systems if synchronous multiprocessor operations are needed and clkin is connected, the header must be minimal. if the skew is too large, synchronous operations may be off by one or more cycles between processors. for synchronous multiprocessor operation tck, tms, clkin and emu should be treated as critical signals in terms of skew, and should be laid out as short as possible on your board. if tck, tms and clkin are driving a large number of adsp-21161 (more than eight) in your system, then treat them as a clock tree using multiple drivers to minimize skew. (see figure 9 ) if synchronous multiprocessor operations are not needed (i.e., clkin is not connected), just use appropriate parallel termination on tck and tms. tdi, tdo, emu and trst are not critical signals in terms of skew. for complete information on the sharc ez-ice, see the adsp-21000 family jtag ez-ice user's guide and reference. system clkin emu 5k ? ? ? ? * tdi tdo 5k ? ? ? ? * tdi emu tm s tc k tdo trst clkin *open drain driver or equivalent, i.e., tdi tdo tdi tdo tdi tdo tdi tdo tdi tdo
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 21 rev. pre adsp-21160-specifications note that component specifications are subject to change without notice. table 4 recommended operating conditions signal k grade parameter min max units v ddint internal (core) supply voltage, 80 mhz 2.37 2.63 v v ddint internal (core) supply voltage, 100 mhz tbd tbd v av dd analog (pll) supply voltage, 80 mhz 2.37 2.63 v av dd analog (pll) supply voltage, 100 mhz tbd tbd v v ddext external (i/o) supply voltage 3.13 3.47 v v ih1 high level input voltage 1 , @ v ddext = max 1. applies to input and bidirectional pins: data63-0, addr31-0, rdx , wrx , ack, sbts , irq2-0 , flag3-0, hbg , cs , dmar1 , dmar2 , br6-1 , id2-0, rpba, pa , brst, tfs0, tfs1, rfs0, rfs1, lxdat3-0, lxclk, lxack, eboot, lboot, bms , tms, tdi, tck, hbr , dr0, dr1, tclk0, tclk1, rclk0, rclk1. 2.0 v ddext +0.5 v v ih2 high level input voltage 2 , @ v ddext = max 2. applies to input pins: clkin, reset , trst . 2.2 v ddext +0.5 v v il low level input voltage 1,2 , @ v ddext = min -0.5 0.8 v t case case operating temperature 3 3. see ? environmental conditions ? on page 59 for information on thermal specifications. 0 +85 c table 5 electrical characteristics parameter test conditions min max units v oh high level output volt- age 1 @ v ddext = min, i oh = -2.0 ma 2 2.4 v v ol low level output voltage 1 @ v ddext = min, i ol = 4.0 ma 2 0.4 v i ih high level input cur- rent 3,4 @ v ddext = max, v in = v dd max 10 a i il low level input current 3 @ v ddext = max, v in = 0 v 10 a i ilp low level input current 4 @ v ddext = max, v in = 0 v 150 a i ozh three-state leakage cur- rent 5,6,7,8 @ v ddext = max, v in = v dd max 10 a i ozl three-state leakage current 5,9 @ v ddext = max, v in = 0 v 10 a
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 22 rev. pre i ozhp three-state leakage current 9 @ v ddext = max, v in = v dd max 350 a i ozlar three-state leakage current 8 @ v ddext = max, v in = 0 v 4.2 ma i ozla three-state leakage cur- rent 10 @ v ddext = max, v in = 1.5 v 350 a i ozls three-state leakage current 6 @ v ddext = max, v in = 0 v 150 a i dd- inpeak supply current (inter- nal) 11 t cclk = 12.5 ns, v ddint = max 1410 ma i dd- inhigh supply current (inter- nal) 12 t cclk = 12.5 ns, v ddint = max 940 ma i dd- inlow supply current (inter- nal) 13 t cclk = 12.5 ns, v ddint = max tbd ma i dd- idle supply current (idle) 14 v ddint = max 90 ma ai dd supply current (analog) 15 @av dd = max 10 ma c in input capacitance 16,17 f in =1 mhz, t case =25 c, v in =2.5v 4.7 pf 1. applies to output and bidirectional pins: data63-0, addr31-0, ms3-0 , rdx , wrx , page, clkout, ack, flag3-0, timexp, hbg , redy, dmag1 , dmag2 , br6-1 , pa , brst, cif , dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat3-0, lxclk, lxack, bms , tdo, emu , icsa. 2. see ? output drive currents ? on page 53 for typical drive current capabilities. 3. applies to input pins: ack, sbts , irq2-0 , hbr , cs , dmar1 , dmar2 , id2-0, rpba, eboot, lboot, clkin, reset , tck. 4. applies to input pins with internal pull-ups: dr0, dr1, trst , tms, tdi. 5. applies to three-statable pins: data63-0, addr31-0, ms3-0 , rdx , wrx , page, clkout, ack, flag3-0, redy, hbg , dmag1 , dmag2 , bms , br6-1 , tfsx, rfsx, tdo, emu . (note that ack is pulled up internally with 2 k ? during reset in a multiprocessor system, when id2-0 = 001 and another adsp-21160 is not requesting bus mastership.) 6. applies to three-statable pins with internal pull-ups: dt0, dt1, tclk0, tclk1, rclk0, rclk1. 7. applies to pa pin. 8. applies to ack pin when pulled up. (note that ack is pulled up internally with 2 k ? during reset in a multiprocessor system, when id2-0 = 001 and another adsp-21160 is not requesting bus mastership). 9. applies to three-statable pins with internal pull-downs: lxdat7-0, lxclk, lxack. 10.applies to ack and cif pins when keeper latch enabled. 11.the test program used to measure i ddinpeak represents worst case processor operation and is not sustainable under normal application conditions. actual internal power measurements made using typical applications are less than specified. for more information, see ? power dissipation ? on page 53. 12.i ddinhigh is a composite average based on a range of high activity code. for more information, see ? power dissipation ? on page 53. 13.i ddinlow is a composite average based on a range of low activity code. for more information, see ? power dissipation ? on page 53. 14.idle denotes adsp-21160 state during execution of idle instruction. for more information, see ? power dissipation ? on page 53. 15.characterized, but not tested. 16.applies to all signal pins. 17.guaranteed, but not tested. table 5 electrical characteristics (continued) parameter test conditions min max units
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 23 rev. pre esd sensitivity caution: esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-21160 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. timing specifications the adsp-21160 ? s internal clock switches at higher frequencies than the system input clock (clkin). to generate the internal clock, the dsp uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the dsp ? s internal clock (the clock source for the external port logic and i/o pads). the adsp-21160 ? s internal clock (a multiple of clkin) provides the clock signal for timing internal memory, processor core, link ports, serial ports, and external port (as required for read/write strobes in asynchronous access mode). during reset, program the ratio between the dsp ? s internal clock frequency and external (clkin) clock frequency with the clk_cfg3-0 pins. even though the internal clock is the clock source for the external port, the external port clock always switches at the clkin frequency. to determine switching frequencies for the serial and link ports, divide down the internal clock, using the programmable divider control of each port (tdivx/rdivx for the serial ports and lxclkd1-0 for the link ports). table 6 absolute maximum ratings 1 parameter absolute maximum rating internal (core) supply voltage (v ddint ) -0.3 v to +3.0 v analog (pll) supply voltage (av dd ) -0.3 v to +3.0 v external (i/o) supply voltage (v ddext ) -0.3 v to +4.6 v input voltage -0.5 v to v ddext + 0.5 v output voltage swing -0.5 v to v ddext + 0.5 v load capacitance 200 pf storage temperature range -65 c to +150 c lead temperature (5 seconds) +185 c 1. stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only, and functio nal oper- ation of the device at these or any other conditions greater than those indicated in the operational sections of this specifica tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. arn in g ed en itive devi e
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 24 rev. pre note the following definitions of various clock periods that are a function of clkin and the appropriate ratio control: t cclk = (t ck ) / cr t lclk = (t cclk ) * lr t sclk = (t cclk ) * sr where: lclk = link port clock sclk = serial port clock t ck = clkin clock period t cclk = (processor) core clock period t lclk = link port clock period t sclk = serial port clock period cr = core/clkin ratio (2, 3, or 4:1, determined by clk_cfg3-0 at reset) lr = link port/core clock ratio (1, 2, 3, or 4:1, determined by lxclkd) sr = serial port/core clock ratio (wide range, determined by xclkdiv) use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 32 under test conditions for voltage reference levels. switching characteristics specify how the processor changes its signals. circuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics describe what the processor will do in a given circumstance. use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices.
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 25 rev. pre figure 10 clock input figure 11 reset table 7 clock input parameter 100 mhz 80 mhz units min max min max timing requirements t ck clkin period 20 100 25 100 ns t ckl clkin width low 8 40 10.5 40 ns t ckh clkin width high 8 40 10.5 40 ns t ckrf clkin rise/fall (0.4v-2.0v) 3 3 ns table 8 reset parameter min max units timing requirements t wrst reset pulse width low 1 1. applies after the power-up sequence is complete. at power-up, the processor's internal phase-locked loop requires no more tha n100 s while reset is low, assuming stable vdd and clkin (not including start-up time of external clock oscillator). 4t ck ns t srst reset setup before clkin high 2 2. only required if multiple adsp-21160s must come out of reset synchronous to clkin with program counters (pc) equal. not re- quired for multiple adsp-21160s communicating over the shared bus (through the external port), because the bus arbitration logi c synchronizes itself automatically after reset. 5ns clkin t ckh t ck t ckl clkin reset t wrst t srst
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 26 rev. pre figure 12 interrupts figure 13 timer table 9 interrupts parameter min max units timing requirements t sir irq2-0 setup before clkin high 1 1. only required for irqx recognition in the following cycle. 6ns t hir irq2-0 hold after clkin high 1 0ns t ipw irq2-0 pulse width 2 2. applies only if t sir and t hir requirements are not met. 2 + t ck ns table 10 timer parameter min max units switching characteristic t dtex clkin high to timexp 17ns clkin irq2-0 t ipw t sir t hir clkin tim ex p t dtex t dtex
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 27 rev. pre figure 14 flags table 11 flags parameter min max units timing requirement t sfi flag3-0in setup before clkin high 1 4ns t hfi flag3-0in hold after clkin high 1 1ns t dwrfi flag3-0in delay after rdx /wrx low 1 tbd ns t hfiwr flag3-0in hold after rdx /wrx deasserted 1 tbd ns switching characteristics t dfo flag3-0out delay after clkin high 9ns t hfo flag3-0out hold after clkin high 1ns t dfoe clkin high to flag3-0out enable 1ns t dfod clkin high to flag3-0out disable 5ns 1. flag inputs meeting these setup and hold times for instruction cycle n will affect conditional instructions in instruction cy cle n+2. clkin fla g 3-0 out fla g o utput clkin rdx , wrx fla g in pu t fla g 3-0 in t dfo t hfo t dfo t dfod t dfoe t sfi t hfi t hfiwr t dwrfi
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 28 rev. pre memory read--bus master use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to clkin. these specifications apply when the adsp-21160 is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rdx , wrx , and dmag strobe timing parameters only apply to asynchronous access mode. table 12 memory read--bus master parameter min max units timing requirements: t dad address, cif , selects delay to data valid 1,2 1. data delay/setup: user must meet t dad , t drld , or t sds. 2. the falling edge of msx , bms is referenced. t ck ? .25t cclk ? 11+w ns t drld rdx low to data valid 1,3 3. note that timing for ack, data, rdx , wrx , and dmag strobe timing parameters only apply to asynchronous access mode. .75t ck ? 11+w ns t hda data hold from address, selects 4 4. data hold: user must meet t hda or t hdrh in asynchronous access mode. see ? example system hold time calculation ? on page 56 for the calculation of hold times given capacitive and dc loads. 0ns t sds data setup to rdx high 2ns t hdrh data hold from rdx high 3,4 1ns t daak ack delay from address, selects 2,5 5. ack delay/setup: user must meet t daak , t dsak , or t sakc for deassertion of ack (low), all three specifications must be met for assertion of ack (high). t ck ? .5t cclk ? 12+w ns t dsak ack delay from rdx low 3,5 t ck ? .75t cclk ? 11+w ns t sakc ack setup to clkin 3,5 .5t cclk +3 ns t hakc ack hold after clkin 3 1ns switching characteristics t drha address, cif , selects hold after rdx high 3 .25t cclk ? 1+h ns t darl address, cif , selects to rdx low 2 .25t cclk ? 1ns t rw rdx pulse width 3 t ck ? .5t cclk ? 1+w ns t rwr rdx high to wrx , rdx , dmagx low 3 .5t cclk ? 1+hi ns w = (number of wait states specified in wait register) t ck . hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). h = t ck (if an address hold cycle occurs as specified in wait register; otherwise h = 0).
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 29 rev. pre figure 15 memory read--bus master wrx , dmag ack data rdx address ms x, cif bms t darl t rw t dad t daak t hdrh t hda t rwr t drld t drha t dsak t sds t sakc t hakc clkin
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 30 rev. pre memory write--bus master use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to clkin. these specifications apply when the adsp-21160 is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rdx , wrx , and dmag strobe timing parameters only apply to asynchronous access mode. table 13 memory write--bus master parameter min max units timing requirements t daak ack delay from address, selects 1,2 1. ack delay/setup: user must meet t daak or t dsak or t sakc for deassertion of ack (low), all three specifications must be met for assertion of ack (high). 2. the falling edge of msx , bms is referenced. t ck ? .5t cclk ? 12+w ns t dsak ack delay from wrx low 1,3 3. note that timing for ack, data, rdx , wrx , and dmag strobe timing parameters only apply to asynchronous access mode. t ck ? .75t cclk ? 11+w ns t sakc ack setup to clkin 1,3 .5t cclk +3 ns t hakc ack hold after clkin 1,3 1ns switching characteristics t dawh address, cif , selects to wrx deasserted 2,3 t ck ? .25t cclk ? 2+w ns t dawl address, cif , selects to wrx low 2 .25t cclk ? 2ns t ww wrx pulse width 3 t ck ? .5t cclk ? 1+w ns t ddwh data setup before wrx high 3 t ck ? .25t cclk ? 12.5+w ns t dwha address hold after wrx deasserted 3 .25t cclk ? 1+h ns t dwhd data hold after wrx deasserted 3 .25t cclk ? 1+h ns t datrwh data disable after wrx deasserted 3,4 4. see ? example system hold time calculation ? on page 56 for calculation of hold times given capacitive and dc loads. .25t cclk ? 1+h .25t cclk +2+h ns t wwr wrx high to wrx , rdx , dmagx low 3 .5t cclk ? 1+hi ns t ddwr data disable before wrx or rdx low .25t cclk ? 1+i ns t wde wrx low to data enabled ? .25t cclk ? 1ns w = (number of wait states specified in wait register) t ck . h = t ck (if an address hold cycle occurs, as specified in wait register; otherwise h = 0). hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). i = t ck (if a bus idle cycle occurs, as specified in wait register; otherwise i = 0).
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 31 rev. pre figure 16 memory write--bus master t datrwh rdx , dmag ack data wrx address ms x , bms , cif t dawl t ww t daak t wwr t wde t ddwr t dw ha t dawh t dsak t ddwh t dw hd t sakc t hakc clkin
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 32 rev. pre synchronous read/write--bus master use these specifications for interfacing to external memory systems that require clkin--relative timing or for accessing a slave adsp-21160 (in multiprocessor memory space). these synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see ? memory read--bus master ? on page 28 and ? memory write--bus master ? on page 30 ). when accessing a slave adsp-21160, these switching characteristics must meet the slave's timing requirements for synchronous read/writes (see ? synchronous read/write--bus slave ? on page 34 ). the slave adsp-21160 must also meet these (bus master) timing requirements for data and acknowledge setup and hold times. table 14 synchronous read/write--bus master parameter min max units timing requirements t ssdati data setup before clkin 1 1. note that timing for ack, data, rdx , wrx , and dmag strobe timing parameters only applies to synchronous access mode. 4.5 ns t hsdati data hold after clkin 1 1ns t sackc ack setup before clkin 1 .5t cclk +3 ns t hackc ack hold after clkin 1 1ns switching characteristics t daddo address, ms x, bms , brst, cif delay after clkin 10 ns t haddo address, ms x, bms , brst, cif hold after clkin 1.5 ns t dpgo page delay after clkin 1.5 11 ns t drdo rdx high delay after clkin 1 .25t cclk ? 1 .25t cclk +9 ns t dwro wrx high delay after clkin 1 .25t cclk ? 1 .25t cclk +9 ns t drwl rdx /wrx low delay after clkin .25t cclk ? 1 .25t cclk +9 ns t ddato data delay after clkin 12.5 ns t hdato data hold after clkin 1.5 ns t dackmo ack delay after clkin 2 2. applies to broadcast write, master precharge of ack. .25t cclk +3 .25t cclk +9 ns t ackmtr ack disable before clkin 2 .25t cclk ? 3ns t dckoo clkout delay after clkin tbd tbd ns t ckop clkout period t ck t ck 3 3. applies only when the dsp drives a bus operation; clkout held inactive or three-state otherwise, for more information, see th e system design chapter in the adsp-21160 sharc dsp technical reference. ns t ckwh clkout width high t ck /2 - 2 t ck /2 + 2 3 ns t ckwl clkout width low t ck /2 - 2 t ck /2 + 2 3 ns
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 33 rev. pre figure 17 synchronous read/write--bus master clkin clkout address ms x, brst , cif ack (in ) pag e rdx data (o ut) wrx data (in ) write cycle read cycle t drw l t hsdati t ssdati t drdo t dw ro t hdato t ddato t drw l t dcko o t ckop t ckwl t haddo t dpgo t sackc t hackc t daddo t ckwh ack (o ut) t dackm o t ackmtr
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 34 rev. pre synchronous read/write--bus slave use these specifications for adsp-21160 bus master accesses of a slave's iop registers or internal memory (in multiprocessor memory space). the bus master must meet these (bus slave) timing requirements. table 15 synchronous read/write--bus slave parameter min max units timing requirements: t saddi address, brst setup before clkin 5ns t haddi address, brst hold after clkin 1ns t srwi rdx /wrx setup before clkin 5ns t hrwi rdx /wrx hold after clkin 1ns t ssdati data setup before clkin 4.5 ns t hsdati data hold after clkin 1ns switching characteristics t ddato data delay after clkin 12.5 ns t hdato data hold after clkin 1.5 ns t dackc ack delay after clkin 10 ns t hacko ack hold after clkin 1.5 ns
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 35 rev. pre figure 18 synchronous read/write--bus slave clkin address ack rdx data (o ut) wrx write access data (in) read access t saddi t haddi t dackc t hacko t hrwi t srwi t ddato t hdato t srwi t hrwi t hsdati t ssdati
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 36 rev. pre multiprocessor bus request and host bus request use these specifications for passing of bus mastership between multiprocessing adsp-21160s (brx ) or a host processor (hbr , hbg ). table 16 multiprocessor bus request and host bus request parameter min max units timing requirements: t hbgrcsv hbg low to rdx /wrx /cs valid 1 tbd tbd ns t shbri hbr setup before clkin 2 6ns t hhbri hbr hold after clkin 2 1ns t shbgi hbg setup before clkin 6ns t hhbgi hbg hold after clkin high 1ns t sbri brx , pa setup before clkin 9ns t hbri brx , pa hold after clkin high 1ns t spai pa setup before clkin 9ns t hpai pa hold after clkin high 1ns t srpbai rpba setup before clkin 6ns t hrpbai rpba hold after clkin 2ns switching characteristics t dhbgo hbg delay after clkin tbd ns t hhbgo hbg hold after clkin tbd ns t dbro brx delay after clkin 8ns t hbro brx hold after clkin 1.5 ns t dpaso pa delay after clkin, slave 8ns t trpas pa disable after clkin, slave 1.5 ns t dpamo pa delay after clkin, master .25t cclk +9 ns t patr pa disable before clkin, master .25t cclk ? 1ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 3 tbd ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 3 tbd ns t ardytr redy (a/d) disable from cs or hbr high 3 tbd ns see notes on page 37
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 37 rev. pre figure 19 multiprocessor bus request and host bus request 1. for first asynchronous access after hbr and cs asserted, addr31-0 must be a non-mms value (tbd) before rdx or wrx goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. see the ? host processor control of the adsp-21160 ? section in the adsp-2116x sharc technical specification. 2. only required for recognition in the current cycle. 3. (o/d) = open drain, (a/d) = active drive. br x (in) t hbri hbr cs rpba redy (o /d) redy (a/d) hbg (o ut) rdx wrx cs o/d = open drain, a/d = active drive t hrpbai t srpbai t drdycs t hbgrcsv t trdyhg t ardytr hbg (in ) t shbgi t hhbgi t sbri clkin hbr hbg (o ut) br x (out) pa (o ut) (sla ve) t hhbri t shbri t hhbgo t dhbgo t dbro t hbro t dpaso t trpa s pa (o ut) (m a ster) t dpam o t patr pa (in ) (o /d) t hpai t spai
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 38 rev. pre asynchronous read/write--host to adsp-21160 use these specifications (continues on page 39 and page 40 ) for asynchronous host processor accesses of an adsp-21160, after the host has asserted cs and hbr (low). after hbg is returned by the adsp-21160, the host can drive the rdx and wrx pins to access the adsp-21160's internal memory or iop registers. hbr and hbg are assumed low for this timing. figure 20 synchronous redy timing table 17 write cycle (synchronous redy) parameter min max units switching characteristics t srdyck redy (o/d) or (a/d) disable to clkin tbd tbd ns clkin redy (o/d) o/d = open drain, a/d = active drive t srdyck redy (a/d)
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 39 rev. pre table 18 read cycle parameter min max units timing requirements t sadrdl address setup/cs low before rdx low 1 0ns t hadrdh address hold/cs hold low after rdx 0ns t wrwh rdx /wrx high width 5ns t drdhrdy rdx high delay after redy (o/d) disable 0ns t drdhrdy rdx high delay after redy (a/d) disable 0ns switching characteristics t sdatrdy data valid before redy disable from low 2ns t drdyrdl redy (o/d) or (a/d) low delay after rdx low 10 ns t rdyprd redy (o/d) or (a/d) low pulse width for read 2t ck ns t hdarwh data disable after rdx high 2 tbd ns 1. not required if rdx and address are valid t hbgrcsv after hbg goes low. for first access after hbr asserted, addr31-0 must be a non-mms value (tbd) before rdx or wrx goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. see the "host processor control of the adsp-21160" section in the adsp-2116x sharc technical specification. redy (o/d) rdx read cycle address/ cs data (out) redy (a/d) t sadrdl t drdyrdl t wrwh t hadrdh t hdarwh t rdyprd t drdhrdy t sdatrdy figure 21 asynchronous read--host to adsp-21160
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 40 rev. pre table 19 write cycle parameter min max units timing requirements t scswrl cs low setup before wrx low 0ns t hcswrh cs low hold after wrx high 0ns t sadwrh address setup before wrx high 5ns t hadwrh address hold after wrx high 2ns t wwrl wrx low width 7ns t wrwh rdx /wrx high width 5ns t dwrhrdy wrx high delay after redy (o/d) or (a/d) disable 0ns t sdatwh data setup before wrx high 5ns t hdatwh data hold after wrx high 1ns switching characteristics t drdywrl redy (o/d) or (a/d) low delay after wrx /cs low 10 ns t rdypwr redy (o/d) or (a/d) low pulse width for write tbd ns o/d = open drain, a/d = active drive redy (o/d) wrx write cycle data (in) address redy (a/d) cs t sdatwh t hdatwh t wwrl t drdywrl t wrwh t hadwrh t rdypwr t dwrhrdy t sadwrh t scswrl t hcswrh figure 22 asynchronous write--host to adsp-21160
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 41 rev. pre three-state timing--bus master, bus slave, hbr, sbts these specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to clkin and the sbts pin. this timing is applicable to bus master transition cycles (btc) and host transition cycles (htc) as well as the sbts pin. table 20 three-state timing--bus slave, hbr , sbts parameter min max units timing requirements t stsck sbts s etup b efore clkin 6ns t htsck sbts h old a fter clkin 1ns switching characteristics t miena a ddress /s elect e nable a fter clkin 1.5 9 ns t miens s trobes e nable a fter clkin 1 1. strobes = rdx , wrx , dmag x. 1.5 5 ns t mienhg hbg e nable a fter clkin 1.5 9 ns t mitra a ddress /s elect d isable a fter clkin .5t ck +1 .5t ck +5 ns t mitrs s trobes d isable a fter clkin 1 t ck ? .25t cclk t ck ? .25t cclk +5 ns t mitrhg hbg d isable a fter clkin 1.5 5 ns t daten d ata e nable a fter clkin 2 2. in addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 1.5 9 ns t dattr d ata d isable a fter clkin 2 1.5 5 ns t acken ack e nable a fter clkin 2 1.5 9 ns t acktr ack d isable a fter clkin 2 1.5 5 ns t cdcen clkout e nable a fter clkin 1.5 9 ns t cdctr clkout d isable a fter clkin .5t ck +1 .5t ck +5 ns t mtrhbg m emory i nterface d isable b efore hbg l ow 3 3. memory interface = address, rdx , wrx , msx , page, dmagx , bms (in eprom boot mode). .5t ck ? 4 tbd ns t menhbg m emory i nterface e nable a fter hbg h igh 3 t ck ? 5 tbd ns
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 42 rev. pre figure 23 three-state timing dma handshake these specifications describe the three dma handshake modes. in all three modes dmar is used to initiate transfers. for handshake mode, dmag controls the latching or enabling of data externally. for external handshake mode, the data transfer is controlled by the addr31-0, rdx , wrx , page, ms3-0 , ack, and dmag signals. for paced master mode, the data transfer is controlled by addr31-0, rdx , wrx , ms3-0 , and ack (not dmag ). for paced master mode, the memory read-bus master, memory write-bus master, and synchronous read/write-bus master timing specifications for addr31-0, rdx , wrx , ms3-0 , page, data63-0, and ack also apply. table 21 dma handshake parameter min max units timing requirements t sdrc dmarx setup before clkin 1 3ns t wdr dmarx width low (nonsynchronous) .5t ck +1 ns t sdatdgl data setup after dmagx low 2 .75t ck ? 7ns t hdatidg data hold after dmagx high 2ns clkin sbts ack memory in terfa ce t mtrhbg hbg m em o ry in terfa c e = a dd ress, rdx , wrx , ms x, cif , hbg , pa g e, dmag x. bms (in eprom boot mode) clkout data memory in terfa ce t menhbg t mitra , t mitrs , t mitrhg t stsck t htsck t dattr t daten t acktr t acken t cdctr t cdce n t miena , t miens , t mienhg
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 43 rev. pre t datdrh data valid after dmarx high 2 tbd ns t dmarll dmarx low edge to low edge 3 t ck ns t dmarh dmarx width high .5t ck +1 ns switching characteristics t ddgl dmagx low delay after clkin .25t cclk +1 .25t cclk +9 ns t wdgh dmagx high width .5t cclk ? 1+hi ns t wdgl dmagx low width t ck ? .5t cclk ? 1ns t hdgc dmagx high delay after clkin t ck ? .25t cclk +1.5 t ck ? .25t cclk +9 ns t vdatdgh data valid before dmagx high 4 t ck ? .25t cclk ? 8t ck ? .25t cclk +5 ns t datrdgh data disable after dmagx high 5 .25t cclk +1.5 .25t cclk +1.5 ns t dgwrl wrx low before dmagx low ? 11 ns t dgwrh dmag x low before wrx high t ck ? .5t cclk ? 2+w ns t dgwrr wrx high before dmagx high 6 ? 11 ns t dgrdl rdx low before dmagx low ? 11 ns t drdgh rdx low before dmagx high t ck ? .5t cclk ? 2+w ns t dgrdr rdx high before dmagx high 6 ? 11 ns t dgwr dmagx high to wrx , rdx , dmagx low .5t cclk ? 1+hi ns t dadgh address/select valid to dmagx high tbd ns t ddgha address/select hold after dmagx high tbd ns w = (number of wait states specified in wait register) t ck . hi = t ck (if data bus idle cycle occurs, as specified in wait register; otherwise hi = 0). 1. only required for recognition in the current cycle. 2. t sdatdgl is the data setup requirement if dmarx is not being used to hold off completion of a write. otherwise, if dmarx low holds off completion of the write, the data can be driven t datdrh after dmarx is brought high. 3. use t dmarll if dmar x transitions synchronous with clkin. otherwise, use t wdr and t dmarh . 4. t vdatdgh is valid if dmarx is not being used to hold off completion of a read. if dmarx is used to prolong the read, then t vdatdgh =t ck ? .25t cclk ? 8+(n t ck ) where n equals the number of extra cycles that the access is prolonged. 5. see ? example system hold time calculation ? on page 56 for calculation of hold times given capacitive and dc loads. 6. this parameter applies for synchronous access mode only. table 21 dma handshake (continued) parameter min max units
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 44 rev. pre figure 24 dma handshake timing clkin t sdrc dmarx data data rdx wrx t wdr t sdrc t dm arh t dm arll t hdgc t wdgh t ddg l dmagx t vdatdgh t datdrh t datrdgh t hdatidg t dgw rl t dgw rh t dgw rr t dgrdl t drdgh t dgrdr t sdatdg l * m em ory read bus master, m em o ry w rite bus m aster, o r synchro nous read/w rite bus m aster timing specifications for addr31-0, rdx , wrx , ms3-0 a n d a c k a ls o a pply h e r e . (e x te r n a l d e v ic e to e x ter n al m e m o r y ) (external memory to external device) tra n sfers betw een a dsp-2116x internal memory and external device transfers between external device and external memory* (external handshake mode) t ddgha address msx , t dadgh t wdgl (fro m external drive to adsp-2116x) (fro m a dsp-2116x to ex tern a l drive)
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 45 rev. pre link ports calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between ldata and lclk. setup skew is the maximum delay that can be introduced in ldata relative to lclk, (setup skew = t lclktwh min ? t dldch ? t sldcl ). hold skew is the maximum delay that can be introduced in lclk relative to ldata, (hold skew = t lclktwl min ? t hldch ? t hldcl ). calculations made directly from speed specifications will result in unrealistically small skew times because they include multiple tester guardbands. the setup and hold skew times shown below are calculated to include only one tester guardband. adsp-21160 setup skew = tbd ns max adsp-21160 hold skew = tbd ns max note that there is a 2 cycle effect latency between the link port enable instruction and the dsp enabling the link port. figure 25 link ports ? receive table 22 link ports receive parameter min max units timing requirements t sldcl data setup before lclk low 2ns t hldcl data hold after lclk low 2ns t lclkiw lclk period t lclk ns t lclkrwl lclk width low 3.5 ns t lclkrwh lclk width high 3.5 ns switching characteristics t dlalc lack low delay after lclk high 1 1. lack goes low with t dlalc relative to rise of lclk after first nibble, but doesn ? t go low if the receiver's link buffer is not about to fill. tbd tbd ns lclk lda t(7:0) la ck (o ut) receive in t sldcl t hldcl t lclkrw h t dlalc t lclkrw l t lclkiw
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 46 rev. pre figure 26 link ports ? transmit table 23 link ports transmit parameter min max units timing requirements t slach lack setup before lclk high 15 ns t hlach lack hold after lclk high ? 2ns switching characteristics t dldch data delay after lclk high 2ns t hldch data hold after lclk high ? 2ns t lclktwl lclk width low .5t lclk ? 1 .5t lclk +1 ns t lclktwh lclk width high .5t lclk ? 1 .5t lclk +1 ns t dlaclk lclk low delay after lack high .5t lclk +5 3t lclk +11 ns lclk lda t(7:0) lac k (in ) th e t slach req uirem en t a pplies to th e risin g edg e o f lc lk o n ly fo r the first n ibble tra n sm itted. tra nsm it last nibble/byte tra n sm itted first nibble/byte tra n sm itted lclk in a ctive (hig h) out t dldch t hldch t lclktw h t lclktw l t slach t hlach t dlaclk
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 47 rev. pre serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay & frame sync setup and hold, 2) data delay & data setup and hold, and 3) sclk width. table 24 serial ports ? external clock parameter min max units timing requirements t sfse tfs/rfs setup before tclk/rclk 1 1. referenced to sample edge. 3.5 ns t hfse tfs/rfs hold after tclk/rclk 1,2 2. rfs hold after rck when mce = 1, mfd = 0 is 0 ns minimum from drive edge. tfs hold after tck for late external tfs is 0 ns minimum from drive edge. 4ns t sdre receive data setup before rclk 1 1.5 ns t hdre receive data hold after rclk 1 4ns t sclkw tclk/rclk width 9ns t sclk tclk/rclk period 2t cclk ns table 25 serial ports ? internal clock parameter min max units timing requirements t sfsi tfs setup before tclk 1 ; rfs setup before rclk 1 1. referenced to sample edge. 8ns t hfsi tfs/rfs hold after tclk/rclk 1,2 2. rfs hold after rck when mce = 1, mfd = 0 is 0 ns minimum from drive edge. tfs hold after tck for late external tfs is 0 ns minimum from drive edge. 1ns t sdri receive data setup before rclk 1 3ns t hdri receive data hold after rclk 1 3ns
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 48 rev. pre table 26 serial ports ? external or internal clock parameter min max units switching characteristics t dfse rfs delay after rclk (internally generated rfs) 1 1. referenced to drive edge. 13 ns t hofse rfs hold after rclk (internally generated rfs) 1 3ns table 27 serial ports ? external clock parameter min max units switching characteristics t dfse tfs delay after tclk (internally gener- ated tfs) 1 1. referenced to drive edge. 13 ns t hofse tfs hold after tclk (internally generated tfs) 1 3ns t ddte transmit data delay after tclk 1 16 ns t hodte transmit data hold after tclk 1 0ns table 28 serial ports ? internal clock parameter min max units switching characteristics t dfsi tfs delay after tclk (internally gener- ated tfs) 1 1. referenced to drive edge. 4.5 ns t hofsi tfs hold after tclk (internally generated tfs) 1 -1.5 ns t ddti transmit data delay after tclk 1 7.5 ns t hdti transmit data hold after tclk 1 0ns t sclkiw tclk/rclk width .5t sclk ? 2.5 .5t sclk +2 ns
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 49 rev. pre table 29 serial ports ? enable and three-state parameter min max units switching characteristics t ddten data enable from external tclk 1 1. referenced to drive edge. 4ns t ddtte data disable from external tclk 1 10 ns t ddtin data enable from internal tclk 1 0ns t ddtti data disable from internal tclk 1 3ns table 30 serial ports ? external late frame sync parameter min max units switching characteristics t ddtlfse data delay from late external tfs or exter- nal rfs with mce = 1, mfd = 0 1 1. mce = 1, tfs enable and tfs valid follow t ddtlfse and t ddtenfs . 13 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 1 3.5 ns
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 50 rev. pre figure 27 serial ports dt dt drive edge drive edge drive edge drive edge tc lk / rc lk tc lk (in t) tc lk / rc lk tc lk (ex t) rclk rfs dr drive edge sample edge da ta receive? intern al clo ck da ta receive? extern al clo ck rclk rfs dr drive edge sample edge n o te: eith er th e risin g edg e o r fa llin g edg e o f rc lk, tc lk c a n be used a s th e a c tive sa m plin g edg e. tc lk tfs dt drive edge sample edge tc lk tfs dt drive edge sample edge da ta tran sm it? internal clo ck data transmit? external clock n o te: eith er th e risin g edg e o r fa llin g edg e o f rc lk, tc lk c a n be used a s th e a c tive sa m plin g edg e. t ddtte t ddten t ddtti t ddtin t sdri t hdri t sfsi t hfsi t dfse t hofse t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse t ddti t hdti t sfsi t hfsi t sclkiw tdfsi t hofsi t ddte t hdte t sfse t hfse t dfse t sclkw t hofse
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 51 rev. pre figure 28 external late frame sync (see note 2) drive sam ple drive tc lk tfs dt drive sam ple drive late externa l tfs external rfs with m ce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs 1st bit 2nd bit (see note 2) t hofse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t hofse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 52 rev. pre figure 29 ieee 11499.1 jtag test access port table 31 jtag test access port and emulation parameter min max units timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5ns t htap tdi, tms hold after tck high 6ns t ssys system inputs setup before tck low 1 7ns t hsys system inputs hold after tck low 1 18 ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 13 ns t dsys system outputs delay after tck low 2 18 ns 1. system inputs = data63-0, addr31-0, rdx , wrx , ack, sbts , hbr , hbg , cs , dmar1 , dmar2 , br6-1 , id2-0, rpba, irq2-0 , flag3-0, pa , brst, dr0, dr1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat7-0, lxclk, lx- ack, eboot, lboot, bms , clkin, reset . 2. system outputs = data63-0, addr31-0, ms3-0 , rdx , wrx , ack, page, clkout, hbg , redy, dmag1 , dmag2 , br6-1 , pa , brst, cif , flag3-0, timexp, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat7-0, lx- clk, lxack, bms . tc k tm s tdi tdo system in puts system outputs t stap t tc k t htap t dtdo t ssys t hsys t dsys
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 53 rev. pre output drive currents figure 33 shows typical i-v characteristics for the output drivers of the adsp-21160. the curves represent the current drive capability of the output drivers as a function of output voltage. power dissipation total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruction execution sequence and the data operands involved. using the current specifications (i ddinpeak , i ddinhigh , i ddinlow , i ddidle ) from table 5 and the current-versus-operation information in table 32 , you can estimate the adsp-21160 ? s internal power supply (v ddint ) input current for a specific application, according to the following formula: %peak i ddinpeak %high i ddinhigh %low i ddinlow +%idle i ddidle i ddint the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: the number of output pins that switch during each cycle (o) the maximum frequency at which they can switch (f) table 32 adsp-21160 operation types versus input current operation peak activity 1 (i ddinpeak ) 1. the state of the peyen bit (simd versus sisd mode) does not influence these calculations. high activity 1 (i ddinhigh ) low activity 1 (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 2. these assume a 2:1 core clock ratio. for more information on ratios and clocks (t ck and t cclk ), see the timing ratio definitions on page 24 . 2 per t ck cycle (dm 64 and pm 64 ) 1 per t ck cycle (dm 64 ) none internal memory dma 1 per 2 t cclk cycles 1 per 2 t cclk cycles 1 per 2 t cclk cycles external memory dma 1 per external port cycle ( 64) 1 per external port cycle ( 64) 1 per external port cycle ( 64) data bit pattern for core memory access and dma worst case random random
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 54 rev. pre their load capacitance (c) their voltage swing (vdd) and is calculated by: pext = o c vdd 2 f the load capacitance should include the processor's package capacitance (cin). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. example: estimate pext with the following assumptions: a system with one bank of external data memory ? asynchronous ram (64-bit) four 64k 16 ram chips are used, each with a load of 10 pf external data memory writes occur every other cycle, a rate of 1/(4t ck ), with 50% of the pins switch- ing the bus cycle time is 50 mhz (t ck = 20 ns). the pext equation is calculated for each class of pins that can drive: a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: p total = p ext + p int + p pll where: p ext is from table 33 p int is i ddint 2.5v, using the calculation i ddint listed in ? power dissipation ? on page 53 p pll is ai dd 2.5v, using the value for ai dd listed in table 5 on page 21 note that the conditions causing a worst-case pext are different from those causing a worst-case pint. maximum pint cannot occur while 100% of the output pins are switching from all ones to all table 33 external power calculations (3.3 v device) pin type # of pins % switching c f vdd 2 = p ext address 15 50 44.7 pf 12.5 mhz 10.9 v = 0.046 w ms0 1 0 44.7 pf 12.5 mhz 10.9 v = 0.000 w wrx 2- 44.7 pf 25 mhz 10.9 v = 0.024 w data 64 50 14.7 pf 12.5 mhz 10.9 v = 0.064 w clkout 1 - 4.7 pf 25 mhz 10.9 v = 0.001 w p ext = 0.135 w
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 55 rev. pre zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 56 rev. pre test conditions output disable time output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, cl and the load current, il. this decay time can be approximated by the following equation: t decay = (c l ? v)/i l the output disable time t dis is the difference between t measured and t decay as shown in figure 25. the time t measured is the interval from when the reference signal switches to when the output voltage decays ? v from the measured output high or output low voltage. t decay is calculated with test loads cl and il, and with ? v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. the output enable time t ena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram (figure 25). if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? v to be the difference between the adsp-21160's output voltage and the input threshold for the device requiring the hold time. a typical ? v will be 0.4 v. cl is the total bus capacitance (per data line), and il is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). figure 30 output enable/disable reference signal t dis o utput sta rts driv in g v oh (measured) - dv v ol (measured) + dv t measured v oh (measured) v ol (measured) 2.0v 1.0v v oh (measured) v ol (measured) high-impedance state. test c o n ditio n s c a use this voltage to be approxim ately 1.5v output stops driv in g t ena t decay
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 57 rev. pre figure 31 equivalent device loading for ac measurements (includes all fixtures) figure 32 voltage reference levels for ac measurements (except output enable/disable) capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 31 ). the delay and hold specifications given should be derated by a factor of 1.5 ns/50 pf for loads other than the nominal value of 50 pf. figures 29-30, 33-34 show how output rise time varies with capacitance. figures 31, 35 show graphically how output delays and holds vary with load capacitance. (note that this graph or derating does not apply to output disable delays; see ? output disable time ? on page 56 .) the graphs of figures 29, 30 and 31 may not be linear outside the ranges shown. figure 33 adsp-21160 typical drive currents +1.5v 50pf to output pin i ol i oh in put or output 1.5v 1.5v source (vddext) voltage - v 120 -20 -80 0 3.5 0.5 1 1.5 2 2.5 3 100 0 -40 -60 60 20 80 40 -100 -120 source (vddext) current - ma 3.47v, 0c 3.3v, +25c 3.13v, +85c v oh 3.13v, +85c 3.3v, +25c 3.47v, 0c v ol
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 58 rev. pre figure 34 typical output rise time (10%-90%, v ddext =max) vs. load capacitance figure 35 typical output rise time (10%-90%, v ddext =min) vs. load capacitance figure 36 typical output delay or hold vs. load capacitance (at max case temperature) load capacitance - pf 16.0 8.0 0 0 200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 fall tim e rise time y = tbd y = tbd rise a nd fa ll tim es - ns (0.35v - 3.12v, 10% - 90 %) 3.5 0 3.0 2.5 2.0 1.5 1.0 0.5 load capacitance - pf 0 200 20 40 60 80 100 120 140 160 180 fall tim e rise time y = tbd y =tbd rise and fall times - ns (0.31 - 2.82, 10% - 90% ) load capacitance - pf 5 - 25 200 50 75 100 125 150 175 4 3 2 1 nominal y = tbd output delay or ho ld - ns
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 59 rev. pre environmental conditions thermal characteristics the adsp-21160 is packaged in a 400-lead plastic ball grid array (pbga). the adsp-21160 is specified for a case temperature (t case ). to ensure that the t case data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. use the center block of ground pins (pbga balls: h8 ? 13, j8 ? 13, k8 ? 13, l8 ? 13, m8 ? 13, and n8 ? 13) to provide thermal pathways to your printed circuit board ? s ground plane. a heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive. t case = t amb + (pd ca ) t case = case temperature (measured on top surface of package) pd = power dissipation in w (this value depends upon the specific application; a method for calculating pd is shown under power dissipation). ca = value from table below. jb = 5.6 c/w notes this represents thermal resistance at total power of 5 w. with air flow, no variance is seen in ca with power. ca at 0 lfm varies with power: at 2w, ca = 14 c/w, at 3 w ca = 11 c/w. jc = 1.7 c/w airflow (linear ft./min.) 0 100 200 400 600 airflow (meters/second) 0 .5 1 2 3 ca ( c/w) 1 1. these are preliminary estimates. 20.7 18 15.3 12.9 10.5
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 60 rev. pre 400-ball metric pbga pin configurations table 34 400-lead metric pbga pin assignments pin name pbga pin# pin name pbga pin# pin name pbga pin# pin name pbga pin# data[14] a01 data[22] b01 data[24] c01 data[28] d01 data[13] a02 data[16] b02 data[18] c02 data[25] d02 data[10] a03 data[15] b03 data[17] c03 data[20] d03 data[8] a04 data[9] b04 data[11] c04 data[19] d04 data[4] a05 data[6] b05 data[7] c05 data[12] d05 data[2] a06 data[3] b06 data[5] c06 vddext d06 tdi a07 data[0] b07 data[1] c07 vddint d07 trst a08 tck b08 tms c08 vddext d08 reset a09 emu b09 td0 c09 vddext d09 rpba a10 irq2 b10 irq1 c10 vddext d10 irq0 a11 flag3 b11 flag2 c11 vddext d11 flag1 a12 flag0 b12 vddext c12 vddext d12 timexp a13 vddext b13 nc c13 vddint d13 vddext a14 nc b14 tclk1 c14 vddext d14 nc a15 dt1 b15 dr1 c15 tfs0 d15 tfs1 a16 rclk1 b16 dr0 c16 l1dat[7] d16 rfs1 a17 rfs0 b17 l0dat[7] c17 l0clk d17 rclk0 a18 tclk0 b18 l0dat[6] c18 l0dat[3] d18 dt0 a19 l0dat[5] b19 l0ack c19 l0dat[1] d19 l0dat[4] a20 l0dat[2] b20 l0dat[0] c20 l1clk d20 data[30] e01 data[34] f01 data[38] g01 data[40] h01 data[29] e02 data[33] f02 data[35] g02 data[39] h02 data[23] e03 data[27] f03 data[32] g03 data[37] h03 data[21] e04 data[26] f04 data[31] g04 data[36] h04 vddext e05 vddext f05 vddext g05 vddext h05 vddint e06 vddint f06 vddint g06 vddint h06 vddint e07 gnd f07 gnd g07 gnd h07 vddint e08 gnd f08 gnd g08 gnd h08 vddint e09 gnd f09 gnd g09 gnd h09 vddint e10 gnd f10 gnd g10 gnd h10
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 61 rev. pre gnd e11 gnd f11 gnd g11 gnd h11 vddint e12 gnd f12 gnd g12 gnd h12 vddint e13 gnd f13 gnd g13 gnd h13 vddint e14 gnd f14 gnd g14 gnd h14 vddint e15 vddint f15 vddint g15 vddint h15 vddext e16 vddext f16 vddext g16 vddext h16 l1dat[6] e17 l1dat[4] f17 l1dat[2] g17 l2dat[5] h17 l1dat[5] e18 l1dat[3] f18 l2dat[6] g18 l2ack h18 l1ack e19 l1dat[0] f19 l2dat[4] g19 l2dat[3] h19 l1dat[1] e20 l2dat[7] f20 l2clk g20 l2dat[1] h20 data[44] j01 clk_cfg_0 k01 clkin l01 avdd m01 data[43] j02 data[46] k02 clk_cfg_1 l02 clk_cfg_3 m02 data[42] j03 data[45] k03 agnd l03 clkout m03 data[41] j04 data[47] k04 clk_cfg_2 l04 gnd m04 vddext j05 vddext k05 vddext l05 vddext m05 vddint j06 vddint k06 vddint l06 vddint m06 gnd j07 gnd k07 gnd l07 gnd m07 gnd j08 gnd k08 gnd l08 gnd m08 gnd j09 gnd k09 gnd l09 gnd m09 gnd j10 gnd k10 gnd l10 gnd m10 gnd j11 gnd k11 gnd l11 gnd m11 gnd j12 gnd k12 gnd l12 gnd m12 gnd j13 gnd k13 gnd l13 gnd m13 gnd j14 gnd k14 gnd l14 gnd m14 vddint j15 vddint k15 vddint l15 vddint m15 vddext j16 vddext k16 vddext l16 vddext m16 l2dat[2] j17 br6 k17 br2 l17 page m17 l2dat[0] j18 br5 k18 br1 l18 sbts m18 hbg j19 br4 k19 ack l19 pa m19 hbr j20 br3 k20 redy l20 l3dat[7] m20 nc n01 data[49] p01 data[53] r01 data[56] t01 nc n02 data[50] p02 data[54] r02 data[58] t02 table 34 400-lead metric pbga pin assignments (continued) pin name pbga pin# pin name pbga pin# pin name pbga pin# pin name pbga pin#
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 62 rev. pre data[48] n03 data[52] p03 data[57] r03 data[59] t03 data[51] n04 data[55] p04 data[60] r04 data[63] t04 vddext n05 vddext p05 vddext r05 vddext t05 vddint n06 vddint p06 vddint r06 vddint t06 gnd n07 gnd p07 gnd r07 vddint t07 gnd n08 gnd p08 gnd r08 vddint t08 gnd n09 gnd p09 gnd r09 vddint t09 gnd n10 gnd p10 gnd r10 vddint t10 gnd n11 gnd p11 gnd r11 vddint t11 gnd n12 gnd p12 gnd r12 vddint t12 gnd n13 gnd p13 gnd r13 vddint t13 gnd n14 gnd p14 gnd r14 vddint t14 vddint n15 vddint p15 gnd r15 vddint t15 vddext n16 vddext p16 vddext r16 vddext t16 l3dat[5] n17 l3dat[2] p17 l4dat[5] r17 l4dat[3] t17 l3dat[6] n18 l3dat[1] p18 l4dat[6] r18 l4ack t18 l3dat[4] n19 l3dat[3] p19 l4dat[7] r19 l4clk t19 l3clk n20 l3ack p20 l3dat[0] r20 l4dat[4] t20 data[61] u01 addr[4] v01 addr[5] w01 addr[8] y01 data[62] u02 addr[6] v02 addr[9] w02 addr[11] y02 addr[3] u03 addr[7] v03 addr[12] w03 addr[13] y03 addr[2] u04 addr[10] v04 addr[15] w04 addr[16] y04 vddext u05 addr[14] v05 addr[17] w05 addr[19] y05 vddext u06 addr[18] v06 addr[20] w06 addr[21] y06 vddext u07 addr[22] v07 addr[23] w07 addr[24] y07 vddext u08 addr[25] v08 addr[26] w08 addr[27] y08 vddext u09 addr[28] v09 addr[29] w09 addr[30] y09 vddext u10 id0 v10 id1 w10 addr[31] y10 vddext u11 addr[1] v11 addr[0] w11 id2 y11 vddext u12 ms1 v12 bms w12 brst y12 vddext u13 cs v13 ms2 w13 ms0 y13 vddext u14 rdl v14 cif w14 ms3 y14 table 34 400-lead metric pbga pin assignments (continued) pin name pbga pin# pin name pbga pin# pin name pbga pin# pin name pbga pin#
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21160 preliminary data sheet january 2000 for current information contact analog devices at (781) 461-3881 63 rev. pre figure 37 400-lead metric pbga pin assignments (bottom view, summary) vddext u15 dmar2 v15 rdh w15 wrh y15 vddext u16 l5dat[0] v16 dmag2 w16 wrl y16 l5dat[7] u17 l5dat[2] v17 lboot w17 dmag1 y17 l4dat[0] u18 l5ack v18 l5dat[1] w18 dmar1 y18 l4dat[1] u19 l5dat[4] v19 l5dat[3] w19 eboot y19 l4dat[2] u20 l5dat[6] v20 l5dat[5] w20 l5clk y20 table 34 400-lead metric pbga pin assignments (continued) pin name pbga pin# pin name pbga pin# pin name pbga pin# pin name pbga pin# vddint vddext gnd* agnd avdd i/o sig n a ls key: * use the center block of ground pins (pbga balls: h8?13, j8?13, k8?13, l8?13, m8?13, and n8?13) to provide thermal pathways to your printed circuit board?s ground plane. 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t
january 2000 adsp-21160 preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 64 rev. pre package dimensions the adsp-21160 comes in a 27mm 27mm, 400 ball pbga package with 20 rows of balls. all dimensions in figure 38 are in millimeters (mm). ordering guide part number 1 1. these parts are packaged in a 400-lead plastic ball grid array (pbga). case temperature range 2 2. parts for the industrial temperature ranges will be available in 2000. instruction rate on-chip sram operating voltage adsp-21160mkb-80 0 c to +85 c 80 mhz 4 mbit 2.5 int/3.3 ext v ADSP-21160MKB-100 0 c to +85 c 100 mhz 4 mbit tbd int/3.3 ext v 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t 1.27 bsc 1.27 bsc 24.13 bsc 24.13 bsc 27.20 27.00 26.80 27.20 27.00 26.80 24.10 24.00 23.90 24.10 24.00 23.90 top view 2.49 2.32 2.15 detail a note the actual position of the ball grid is within 0.30mm of its ideal position relative to the package edges. the actual position of each ball is within 0.10m m of its ideal position relative to the ball grid. seating plane 1.19 1.17 1.15 0.20 max detail a 0.90 0.75 0.60 ball diameter 0.60 0.55 0.50 0.70 0.60 0.50 figure 38 package dimensions metric 27mm 27mm, 400 ball pbga

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